High performance quaternary logic designs using GNFETs
The implementations of quaternary circuit schematics are presented in this paper. The quaternary logic is a better choice over the conventional logics because it offers high operating speed, reduced chip area and reduced on-chip interconnects. A new method is presented to design quaternary schematic...
保存先:
| 主要な著者: | , |
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| フォーマット: | Artigo |
| 言語: | Inglês |
| 出版事項: |
Elsevier
2023-09-01
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| シリーズ: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| 主題: | |
| オンライン･アクセス: | http://www.sciencedirect.com/science/article/pii/S277267112300092X |
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