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Power efficient and high performance VLSI architecture for AES algorithm

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high perf...

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Principais autores: K. Kalaiselvi, H. Mangalam
Format: Artigo
Sprog:Inglês
Udgivet: SpringerOpen 2015-09-01
Serier:Journal of Electrical Systems and Information Technology
Fag:
Advanced encryption standard (AES) algorithm
VLSI architecture
Low power
FPGA implementation
Online adgang:http://www.sciencedirect.com/science/article/pii/S2314717215000380
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