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Power efficient and high performance VLSI architecture for AES algorithm

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high perf...

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Guardado en:
Autores principales: K. Kalaiselvi, H. Mangalam
Formato: Artigo
Lenguaje:Inglês
Publicado: SpringerOpen 2015-09-01
Colección:Journal of Electrical Systems and Information Technology
Materias:
Advanced encryption standard (AES) algorithm
VLSI architecture
Low power
FPGA implementation
Acceso en línea:http://www.sciencedirect.com/science/article/pii/S2314717215000380
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