Power efficient and high performance VLSI architecture for AES algorithm
Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high perf...
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| Autors principals: | , |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
SpringerOpen
2015-09-01
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| Col·lecció: | Journal of Electrical Systems and Information Technology |
| Matèries: | |
| Accés en línia: | http://www.sciencedirect.com/science/article/pii/S2314717215000380 |
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