Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter u...

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Prif Awduron:	Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
Fformat:	Artigo
Iaith:	Inglês
Cyhoeddwyd:	Wiley 2021-01-01
Cyfres:	IET Computers & Digital Techniques
Pynciau:	counting circuits logic design multiplying circuits
Mynediad Ar-lein:	https://doi.org/10.1049/cdt2.12002
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!