A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS
In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a...
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| Principais autores: | , , |
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| 格式: | Artigo |
| 語言: | Inglês |
| 出版: |
Scientific Research Support Fund of Jordan (SRSF) and Princess Sumaya University for Technology (PSUT)
2019-08-01
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| 叢編: | Jordanian Journal of Computers and Information Technology |
| 主題: | |
| 在線閱讀: | http://jjcit.org/Volume%2005,%20Number%2002/8-DOI%2010.5455-jjcit.71-1556375171.pdf |
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