Delay Insensitive Ternary CMOS Logic for Secure Hardware
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). Th...
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| Asıl Yazarlar: | , , |
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| Materyal Türü: | Artigo |
| Dil: | Inglês |
| Baskı/Yayın Bilgisi: |
MDPI AG
2015-09-01
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| Seri Bilgileri: | Journal of Low Power Electronics and Applications |
| Konular: | |
| Online Erişim: | http://www.mdpi.com/2079-9268/5/3/183 |
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