Delay Insensitive Ternary CMOS Logic for Secure Hardware
As digital circuit design continues to evolve due to progress of semiconductor processes well into the sub 100 nm range, clocked architectures face limitations in a number of cases where clockless asynchronous architectures generate less noise and produce less electro-magnetic interference (EMI). Th...
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| Autori principali: | , , |
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| Natura: | Artigo |
| Lingua: | Inglês |
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MDPI AG
2015-09-01
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| Serie: | Journal of Low Power Electronics and Applications |
| Soggetti: | |
| Accesso online: | http://www.mdpi.com/2079-9268/5/3/183 |
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