Low-latency hierarchical routing of reconfigurable neuromorphic systems
A reconfigurable hardware accelerator implementation for spiking neural network (SNN) simulation using field-programmable gate arrays (FPGAs) is promising and attractive research because massive parallelism results in better execution speed. For large-scale SNN simulations, a large number of FPGAs a...
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| Hauptverfasser: | , , , |
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| Format: | Artigo |
| Sprache: | Inglês |
| Veröffentlicht: |
Frontiers Media S.A.
2025-02-01
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| Schriftenreihe: | Frontiers in Neuroscience |
| Schlagworte: | |
| Online-Zugang: | https://www.frontiersin.org/articles/10.3389/fnins.2025.1493623/full |
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