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Low-latency hierarchical routing of reconfigurable neuromorphic systems

A reconfigurable hardware accelerator implementation for spiking neural network (SNN) simulation using field-programmable gate arrays (FPGAs) is promising and attractive research because massive parallelism results in better execution speed. For large-scale SNN simulations, a large number of FPGAs a...

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Principais autores: Samalika Perera, Ying Xu, André van Schaik, Runchun Wang
Format: Artigo
Sprog:Inglês
Udgivet: Frontiers Media S.A. 2025-02-01
Serier:Frontiers in Neuroscience
Fag:
neuromorphic engineering
FPGA acceleration
multi-FPGA
networks on chip
transceivers
SNN
Online adgang:https://www.frontiersin.org/articles/10.3389/fnins.2025.1493623/full
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