Low-latency hierarchical routing of reconfigurable neuromorphic systems

A reconfigurable hardware accelerator implementation for spiking neural network (SNN) simulation using field-programmable gate arrays (FPGAs) is promising and attractive research because massive parallelism results in better execution speed. For large-scale SNN simulations, a large number of FPGAs a...

Celý popis

Podrobná bibliografie

Hlavní autoři:	Samalika Perera, Ying Xu, André van Schaik, Runchun Wang
Médium:	Artigo
Jazyk:	Inglês
Vydáno:	Frontiers Media S.A. 2025-02-01
Edice:	Frontiers in Neuroscience
Témata:	neuromorphic engineering FPGA acceleration multi-FPGA networks on chip transceivers SNN
On-line přístup:	https://www.frontiersin.org/articles/10.3389/fnins.2025.1493623/full
Tagy:	Přidat tag Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!