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Integration scheme of nanoscale resistive switching memory using bottom-up processes at room temperature for high-density memory applications
A facile and versatile scheme is demonstrated to fabricate nanoscale resistive switching memory devices that exhibit reliable bipolar switching behavior. A solution process is used to synthesize the copper oxide layer into 250-nm via-holes that had been patterned in Si wafers. Direct bottom-up filli...
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| Vydáno v: | Sci Rep |
|---|---|
| Hlavní autoři: | , |
| Médium: | Artigo |
| Jazyk: | Inglês |
| Vydáno: |
Nature Publishing Group
2016
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| Témata: | |
| On-line přístup: | https://ncbi.nlm.nih.gov/pmc/articles/PMC4929478/ https://ncbi.nlm.nih.gov/pubmed/27364856 https://ncbi.nlm.nih.govhttp://dx.doi.org/10.1038/srep28966 |
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