Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs
The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed...
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| Autors principals: | , |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
MDPI AG
2020-09-01
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| Col·lecció: | Micromachines |
| Matèries: | |
| Accés en línia: | https://www.mdpi.com/2072-666X/11/10/887 |
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