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CNTFET-based SRAM cell design using INDEP technique

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube f...

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Váldodahkkit: Mehwish Maqbool, Vijay Kumar Sharma, Neeraj Kaushik
Materiálatiipa: Artigo
Giella:Inglês
Almmustuhtton: Elsevier 2024-03-01
Ráidu:e-Prime: Advances in Electrical Engineering, Electronics and Energy
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Liŋkkat:http://www.sciencedirect.com/science/article/pii/S2772671124000597
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