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On the Design and Implementation and Evaluation of Euclidean Geometry Quasi-Cyclic LDPC Codes for NAND Flash Memories

As data storage demands continue to grow, ensuring the reliability of NAND flash devices after a large number of Program/Erase (P/E) cycles have elapsed has become a critical requirement. With an addition in the number of Program/Erase (P/E) cycles in NAND flash devices, it is observed that there is...

Ausführliche Beschreibung

Gespeichert in:
Hauptverfasser: G. Achala, U. Shripathi Acharya, Pathipati Srihari, Linga Reddy Cenkeramaddi
Format: Artigo
Sprache:Inglês
Veröffentlicht: IEEE 2026-01-01
Schriftenreihe:IEEE Open Journal of the Communications Society
Schlagworte:
Error control code
memory device
NAND flash
LDPC codes
QC-LDPC
EG-LDPC
Online-Zugang:https://ieeexplore.ieee.org/document/11535461/
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