Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization
In this paper, a Digital Phase-Locked Loop (DPLL) for GPS synchronization is designed, implemented and tested. It consists of a Phase Frequency Detector (PFD), an RC Low-Pass Filter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO). The analysis, design, and examination of each block are...
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| Autori principali: | , , , , |
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| Natura: | Artigo |
| Lingua: | Inglês |
| Pubblicazione: |
Laboratory of Signals and Systems
2025-03-01
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| Serie: | Algerian Journal of Signals and Systems |
| Soggetti: | |
| Accesso online: | https://ajss.dz/index.php/ajss/article/view/233 |
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