Design and Implementation of a Digital Phase Locked Loop for GPS Synchronization

In this paper, a Digital Phase-Locked Loop (DPLL) for GPS synchronization is designed, implemented and tested. It consists of a Phase Frequency Detector (PFD), an RC Low-Pass Filter (LPF), and a Relaxation Voltage Controlled Oscillator (VCO). The analysis, design, and examination of each block are...

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Principais autores:	Mouloud CHALLAL, Abderrahmane OUADI, Hamid BENTARZI, Abderazak CHERFI, Omar SAIDI
Format:	Artigo
Jezik:	Inglês
Izdano:	Laboratory of Signals and Systems 2025-03-01
Serija:	Algerian Journal of Signals and Systems
Teme:	Digital Phase-Locked Loop, Phase Frequency Detector, RC Low-Pass Filter, Relaxation Voltage Controlled Oscillator
Online dostop:	https://ajss.dz/index.php/ajss/article/view/233
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