Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems

Over the years, significant work has been done on high-integrity systems, such as those found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system failure, thus having functional safety as a key requirement. In this study, we employ an innovative approach to har...

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Autors principals:	Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
Format:	Artigo
Idioma:	Inglês
Publicat:	IEEE 2024-01-01
Col·lecció:	IEEE Access
Matèries:	Circuit faults digital integrated circuits fault detection fault tolerant computing field programmable gate arrays microprocessors
Accés en línia:	https://ieeexplore.ieee.org/document/10589631/
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