Dynamic Triple Modular Redundancy in Interleaved Hardware Threads: An Alternative Solution to Lockstep Multi-Cores for Fault-Tolerant Systems

Over the years, significant work has been done on high-integrity systems, such as those found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system failure, thus having functional safety as a key requirement. In this study, we employ an innovative approach to har...

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Bibliografische gegevens

Hoofdauteurs:	Marcello Barbirotta, Francesco Menichelli, Abdallah Cheikh, Antonio Mastrandrea, Marco Angioli, Mauro Olivieri
Formaat:	Artigo
Taal:	Inglês
Gepubliceerd in:	IEEE 2024-01-01
Reeks:	IEEE Access
Onderwerpen:	Circuit faults digital integrated circuits fault detection fault tolerant computing field programmable gate arrays microprocessors
Online toegang:	https://ieeexplore.ieee.org/document/10589631/
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