Carregant...
A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs e...
Guardat en:
| Publicat a: | Nanoscale Res Lett |
|---|---|
| Autors principals: | , , , , |
| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
Springer US
2017
|
| Matèries: | |
| Accés en línia: | https://ncbi.nlm.nih.gov/pmc/articles/PMC5472634/ https://ncbi.nlm.nih.gov/pubmed/28622720 https://ncbi.nlm.nih.govhttp://dx.doi.org/10.1186/s11671-017-2191-9 |
| Etiquetes: |
Afegir etiqueta
Sense etiquetes, Sigues el primer a etiquetar aquest registre!
|