Parallel Direct Digital Synthesis Architecture for Wideband Multi-GHz Chirp Generation

This paper presents generalized parallel-thread Direct Digital Synthesis (PDDS) architectures for high-frequency and wideband chirp signal generation that exceeds the nominal Nyquist limit imposed by the system clock in conventional single-thread Digital Direct Synthesis (DDS) implementations. An an...

詳細記述

書誌詳細

主要な著者:	Aditya Parikshit Khachane, Priyank Atri, Sonu Panchal, Kankan Deka, Ravi Saini, Govind Prasad
フォーマット:	Artigo
言語:	Inglês
出版事項:	IEEE 2026-01-01
シリーズ:	IEEE Access
主題:	Direct digital synthesis (DDS) chirp signal generation FPGA implementation parallel DDS architecture radar waveform generation wideband signal synthesis
オンライン･アクセス:	https://ieeexplore.ieee.org/document/11613962/
タグ:	タグ追加 タグなし, このレコードへの初めてのタグを付けませんか!