Parallel Direct Digital Synthesis Architecture for Wideband Multi-GHz Chirp Generation

This paper presents generalized parallel-thread Direct Digital Synthesis (PDDS) architectures for high-frequency and wideband chirp signal generation that exceeds the nominal Nyquist limit imposed by the system clock in conventional single-thread Digital Direct Synthesis (DDS) implementations. An an...

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Bibliografische Detailangaben

Hauptverfasser:	Aditya Parikshit Khachane, Priyank Atri, Sonu Panchal, Kankan Deka, Ravi Saini, Govind Prasad
Format:	Artigo
Sprache:	Inglês
Veröffentlicht:	IEEE 2026-01-01
Schriftenreihe:	IEEE Access
Schlagworte:	Direct digital synthesis (DDS) chirp signal generation FPGA implementation parallel DDS architecture radar waveform generation wideband signal synthesis
Online-Zugang:	https://ieeexplore.ieee.org/document/11613962/
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