Static power model for CMOS and FPGA circuits

Abstract In Ultra‐Low‐Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time‐consuming Spice simulations are used to measure the static power consumption. Herein, a technology‐independent static power estimatio...

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Bibliografiset tiedot
Päätekijät:	Anas Razzaq, Andy Ye
Aineistotyyppi:	Artigo
Kieli:	Inglês
Julkaistu:	Wiley 2021-07-01
Sarja:	IET Computers & Digital Techniques
Aiheet:	CMOS logic circuits field programmable gate arrays integrated circuit modelling logic design low‐power electronics power consumption
Linkit:	https://doi.org/10.1049/cdt2.12021
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Static power model for CMOS and FPGA circuits

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