Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width

In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall...

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Autors principals:	Sanguk Lee, Jinsu Jeong, Jongseo Park, Seunghwan Lee, Junjong Lee, Yonghwan Ahn, Minchan Kim, Rock-Hyun Baek
Format:	Artigo
Idioma:	Inglês
Publicat:	IEEE 2025-01-01
Col·lecció:	IEEE Access
Matèries:	Forksheet field-effect transistors (FSFETs) nanosheet FETs (NSFETs) patterned wall cell height (CH) performance optimization technology computer-aided design (TCAD)
Accés en línia:	https://ieeexplore.ieee.org/document/11021571/
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