Low-Power, Low-Energy, Static, Contention-Free, TSPC Dual-Edge Triggered Flip-Flops
The dual edge-triggered flip-flop samples the data on both the positive and negative edges of the clock. Hence, it can lead to lower clock relative power consumption as compared to the single-edge triggered flip-flop while maintaining the same data throughput. In this paper, we present two low-power...
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| Hauptverfasser: | , |
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| Format: | Artigo |
| Sprache: | Inglês |
| Veröffentlicht: |
IEEE
2025-01-01
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| Schriftenreihe: | IEEE Access |
| Schlagworte: | |
| Online-Zugang: | https://ieeexplore.ieee.org/document/10965666/ |
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