An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS

As essential building blocks of sequential digital circuits, optimizing the power consumption of flip-flops (FFs) can significantly reduce the total energy of digital systems. This paper proposes an ultra-low power 25-transistor (29-T with reset function) true single-phase clocked (TSPC) flip-flop b...

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Hlavní autoři:	Jiliang Liu, Huidong Zhao, Zhi Li, Kangning Wang, Shushan Qiao
Médium:	Artigo
Jazyk:	Inglês
Vydáno:	IEEE 2024-01-01
Edice:	IEEE Access
Témata:	CMOS digital circuits flip-flop (FF) low voltage operation ultra-low-power true-single-phase-clocked (TSPC)
On-line přístup:	https://ieeexplore.ieee.org/document/10606254/
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