Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications

In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, w...

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Autors principals:	Talib Al-Ameri, Vihar P. Georgiev, Fikru Adamu-Lema, Asen Asenov
Format:	Artigo
Idioma:	Inglês
Publicat:	IEEE 2017-01-01
Col·lecció:	IEEE Journal of the Electron Devices Society
Matèries:	Nanowire transistor TCAD Monte Carlo vertically stacked
Accés en línia:	https://ieeexplore.ieee.org/document/8046149/
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