AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

As open-source RISC-V cores continue to be released, the development of low-power multicore processors utilizing these cores is invigorating the edge/IoT device market. Nevertheless, comprehensive research on developing low-power multicore processors with integrated security features using existing...

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主要な著者:	Eunjin Choi, Jina Park, Kyuseung Han, Woojoo Lee
フォーマット:	Artigo
言語:	Inglês
出版事項:	Elsevier 2024-12-01
シリーズ:	Engineering Science and Technology, an International Journal
主題:	Edge device AES RISC-V Embedded processor Multi-core processor architecture FPGA prototyping
オンライン･アクセス:	http://www.sciencedirect.com/science/article/pii/S2215098624002805
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