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Research and Implementation of Performance Optimization Methods for RISC-V Level-5 Processors

The widespread adoption of fifth-generation Reduced Instruction Set Computing (RISC-V) processors in embedded systems has driven advancements in domestic processor design. However, research on processor performance optimization methods predominantly focuses on two- to three-stage pipeline architectu...

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Principais autores: Zhiwei Jin, Tingpeng Hu, Zhiyi Jie, Peng Wang
פורמט: Artigo
שפה:Inglês
יצא לאור: MDPI AG 2025-10-01
סדרה:Applied Sciences
נושאים:
RISC-V
5-stage pipeline architecture
CoreMark
processor optimization
embedded processor
גישה מקוונת:https://www.mdpi.com/2076-3417/15/21/11634
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