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Deep Reinforcement Learning Acceleration for Real-Time Edge Computing Mixed Integer Programming Problems

In this work, we present the design and implementation of an ultra-low latency Deep Reinforcement Learning (DRL) FPGA based accelerator for addressing hard real-time Mixed Integer Programming problems. The accelerator exhibits ultra-low latency performance for both training and inference operations,...

Ausführliche Beschreibung

Gespeichert in:
Hauptverfasser: Gerasimos Gerogiannis, Michael Birbas, Aimilios Leftheriotis, Eleftherios Mylonas, Nikolaos Tzanis, Alexios Birbas
Format: Artigo
Sprache:Inglês
Veröffentlicht: IEEE 2022-01-01
Schriftenreihe:IEEE Access
Schlagworte:
Accelerator
deep reinforcement learning
edge computing
FPGA
high level synthesis
mixed integer programming
Online-Zugang:https://ieeexplore.ieee.org/document/9696340/
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