A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL
The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this issue within the context of a Time-to-Digital...
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| Autors principals: | , , , , |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
IEEE
2024-01-01
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| Col·lecció: | IEEE Access |
| Matèries: | |
| Accés en línia: | https://ieeexplore.ieee.org/document/10759641/ |
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