Asynchronous SAR ADC with self‐timed track‐and‐hold
Abstract This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolong...
में बचाया:
| मुख्य लेखकों: | , , , , |
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| स्वरूप: | Artigo |
| भाषा: | Inglês |
| प्रकाशित: |
Wiley
2023-11-01
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| श्रृंखला: | Electronics Letters |
| विषय: | |
| ऑनलाइन पहुंच: | https://doi.org/10.1049/ell2.13026 |
| टैग: |
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