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A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this issue within the context of a Time-to-Digital...

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Principais autores: Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff
Format: Artigo
Sprog:Inglês
Udgivet: IEEE 2024-01-01
Serier:IEEE Access
Fag:
ADC
jitter calibration
ADPLL
non-uniform sampling
interpolation algorithm
digital signal processing
Online adgang:https://ieeexplore.ieee.org/document/10759641/
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