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Parallel Timing-driven Placement Algorithm for FPGA

Traditional timing-driven Field Programmable Gate Array(FPGA) placement algorithm has some degree of error when calculating timing cost.Some timing-driven algorithms achieve better placement quality with a sacrifice of time.To deal with this problem,this paper proposes a timing-driven parallel algor...

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Hovedforfatter: ZHANG Jiaqi,SHEN Jianliang,ZHU Ke
Format: Artigo
Sprog:Inglês
Udgivet: Editorial Office of Computer Engineering 2017-02-01
Serier:Jisuanji gongcheng
Fag:
field programmable gate array(fpga)|simulated annealing algorithm|parallel algorithm|transactional memory(tm)|timing-driven placement
Online adgang:https://www.ecice06.com/fileup/1000-3428/PDF/201702017.pdf
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