High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity. High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis. S...
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| Autors principals: | , , |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
Wiley
2011-01-01
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| Col·lecció: | International Journal of Reconfigurable Computing |
| Accés en línia: | http://dx.doi.org/10.1155/2011/406857 |
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