Design Techniques for High-Speed Wireline Transmitters
Wireline transmitters operating at tens of gigabits per second pose challenging design issues ranging from limited bandwidths to severe sensitivity to jitter. This paper presents a number of analog and digital circuit techniques that allow data rates as high as 80 Gb/s in 45-nm CMOS technology. A PA...
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| Autor principal: | |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
IEEE
2021-01-01
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| Col·lecció: | IEEE Open Journal of the Solid-State Circuits Society |
| Matèries: | |
| Accés en línia: | https://ieeexplore.ieee.org/document/9536949/ |
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