A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor☆

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Flo...

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Detalhes bibliográficos

Principais autores:	Thinh Dang Cong, Phuc Ton That Bao, Trang Hoang
Formato:	Artigo
Idioma:	Inglês
Publicado em:	Elsevier 2023-04-01
coleção:	Ain Shams Engineering Journal
Assuntos:	Floating-gate MOS Flash memory cell Tunneling effects CMOS technology Gate leakage current TCAD tool
Acesso em linha:	http://www.sciencedirect.com/science/article/pii/S2090447922002283
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