Inner Gate Length Modulation of MFMIS Nanosheet FET Memory for Advanced Technology Nodes

This work proposes a new way of lowering the area ratio (AR) between the ferroelectric and metal-oxide-semiconductor (MOS) regions of metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric field-effect transistors (FeFETs): the inner gate length (<inline-formula> <tex-math notation=...

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Principais autores:	Kyoung Min Choi, Jae Seung Woo, Woo Young Choi
Formato:	Artigo
Idioma:	Inglês
Publicado:	IEEE 2025-01-01
Series:	IEEE Access
Assuntos:	Area ratio (AR) ferroelectric field-effect transistor (FeFET) nanosheet field-effect transistor (NSFET) memory window (MW) metal-ferroelectric-metal-insulator-semiconductor (MFMIS)
Acceso en liña:	https://ieeexplore.ieee.org/document/11141383/
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