A high level implementation and performance evaluation of level-I asynchronous cache on FPGA
To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50%) of processors. This paper presents a high level imp...
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| Principais autores: | , , |
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| 格式: | Artigo |
| 語言: | Inglês |
| 出版: |
Springer
2017-07-01
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| 叢編: | Journal of King Saud University: Computer and Information Sciences |
| 主題: | |
| 在線閱讀: | http://www.sciencedirect.com/science/article/pii/S1319157815001056 |
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