Design and Evaluation of Buffered Triple Modular Redundancy in Interleaved-Multi-Threading Processors

Fault management in digital chips is a crucial aspect of functional safety. Significant work has been done on gate and microarchitecture level triple modular redundancy, and on functional redundancy in multi-core and simultaneous-multi-threading processors, whereas little has been done to quantify t...

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Detalles Bibliográficos

Principais autores:	Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Mauro Olivieri
Formato:	Artigo
Idioma:	Inglês
Publicado:	IEEE 2022-01-01
Series:	IEEE Access
Assuntos:	Circuit faults digital integrated circuits fault detection fault tolerant computing field programmable gate arrays microprocessors
Acceso en liña:	https://ieeexplore.ieee.org/document/9968000/
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