Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation
In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an...
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| Autori principali: | , |
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| Natura: | Artigo |
| Lingua: | Inglês |
| Pubblicazione: |
IEEE
2023-01-01
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| Serie: | IEEE Access |
| Soggetti: | |
| Accesso online: | https://ieeexplore.ieee.org/document/10098567/ |
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