500 MS/s 4-Bit Flash ADC with Complementary Architecture
This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 Vpp operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and prea...
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| Principais autores: | , , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado: |
The Korean Institute of Electromagnetic Engineering and Science
2024-01-01
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| Series: | Journal of Electromagnetic Engineering and Science |
| Assuntos: | |
| Acceso en liña: | https://www.jees.kr/upload/pdf/jees-2024-1-r-209.pdf |
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