500 MS/s 4-Bit Flash ADC with Complementary Architecture
This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 Vpp operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and prea...
Spremljeno u:
| Glavni autori: | , , , , |
|---|---|
| Format: | Artigo |
| Jezik: | Inglês |
| Izdano: |
The Korean Institute of Electromagnetic Engineering and Science
2024-01-01
|
| Serija: | Journal of Electromagnetic Engineering and Science |
| Teme: | |
| Online pristup: | https://www.jees.kr/upload/pdf/jees-2024-1-r-209.pdf |
| Oznake: |
Bez oznaka, Budi prvi tko označuje ovaj zapis!
|