Subtractive-Dither-Assisted Background Calibration for Linearity Enhancement in Pipelined ADCs for IIoT Applications

This paper presents a subtractive-dither-assisted background calibration technique for a 2 GS/s 12 bit pipelined analog-to-digital converter (ADC). A large 7 bit pseudo-random dither is injected in both the flash and the multiplying digital-to-analog converter (MDAC) to decorrelate the differential...

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Váldodahkkit:	Shang Xu, Shuwen Liang, Jinbin Li, Zhenxi Kang, Daolin Zhang, Guoan Wu, Lamin Zhan
Materiálatiipa:	Artigo
Giella:	Inglês
Almmustuhtton:	MDPI AG 2026-03-01
Ráidu:	Sensors
Fáttát:	pipelined analog-to-digital converters background calibration nonlinearity dither linear-feedback shift register inter-stage amplifier
Liŋkkat:	https://www.mdpi.com/1424-8220/26/5/1632
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