Subtractive-Dither-Assisted Background Calibration for Linearity Enhancement in Pipelined ADCs for IIoT Applications

This paper presents a subtractive-dither-assisted background calibration technique for a 2 GS/s 12 bit pipelined analog-to-digital converter (ADC). A large 7 bit pseudo-random dither is injected in both the flash and the multiplying digital-to-analog converter (MDAC) to decorrelate the differential...

全面介紹

書目詳細資料

Principais autores:	Shang Xu, Shuwen Liang, Jinbin Li, Zhenxi Kang, Daolin Zhang, Guoan Wu, Lamin Zhan
格式:	Artigo
語言:	Inglês
出版:	MDPI AG 2026-03-01
叢編:	Sensors
主題:	pipelined analog-to-digital converters background calibration nonlinearity dither linear-feedback shift register inter-stage amplifier
在線閱讀:	https://www.mdpi.com/1424-8220/26/5/1632
標簽:	添加標簽 沒有標簽, 成為第一個標記此記錄!