Generative AI Assertions in UVM-Based System Verilog Functional Verification

This paper investigates the potential of leveraging artificial intelligence to automate and optimize the verification process, particularly in generating System Verilog assertions for an Advance Peripheral Bus verification environment using Universal Verification Methodology. Generative artificial i...

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Prif Awduron:	Valentin Radu, Diana Dranga, Catalin Dumitrescu, Alina Iuliana Tabirca, Maria Cristina Stefan
Fformat:	Artigo
Iaith:	Inglês
Cyhoeddwyd:	MDPI AG 2024-09-01
Cyfres:	Systems
Pynciau:	System Verilog ChatGPT Universal Verification Methodology System-on-Chip Large Language Models
Mynediad Ar-lein:	https://www.mdpi.com/2079-8954/12/10/390
Tagiau:	Ychwanegu Tag Dim Tagiau, Byddwch y cyntaf i dagio'r cofnod hwn!