A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS
This paper presents a 12-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) for low-power wireless and imaging systems. A split-capacitor digital-to-analog converter (CDAC) structure is adopted for reducing the core area and improving the sampling spe...
I tiakina i:
| Ngā kaituhi matua: | , , , , , , , |
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| Hōputu: | Artigo |
| Reo: | Inglês |
| I whakaputaina: |
IEEE
2021-01-01
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| Rangatū: | IEEE Access |
| Ngā marau: | |
| Urunga tuihono: | https://ieeexplore.ieee.org/document/9429217/ |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
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