A 12-Bit 2 GS/s Single-Channel High Linearity Pipelined ADC in 40 nm CMOS

This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages...

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Detalles Bibliográficos

Principais autores:	Feitong Wu, Xuan Guo, Hanbo Jia, Xiuheng Wu, Zeyu Li, Ben He, Danyu Wu, Xinyu Liu
Formato:	Artigo
Idioma:	Inglês
Publicado:	MDPI AG 2023-06-01
Series:	Micromachines
Assuntos:	single channel pipelined analog-to-digital converter(ADC) high linearity wide bandwidth
Acceso en liña:	https://www.mdpi.com/2072-666X/14/7/1291
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