A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process

A sub-sampling PLL (SSPLL) with a pulser-free continuous charge pump (CCP) and a bootstrap sampling front-end has been developed and the reference spurs can be significantly suppressed by eliminating cyclic high impedance charge pump operation. A counter-based frequency-locked loop with a fine-tunab...

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التفاصيل البيبلوغرافية
المؤلفون الرئيسيون:	Sangwon Kim, Kihoon Kwon, Minseo Park, Jinhyuk Ahn, Junseo Kim, Joonho Gil, Chulhyun Park, Yunseong Eo, Ramesh Harjani, Taehyoun Oh
التنسيق:	Artigo
اللغة:	Inglês
منشور في:	IEEE 2025-01-01
سلاسل:	IEEE Access
الموضوعات:	Complementary metal-oxide-semiconductor (CMOS) continuous charge pump (CCP) dead zones (DZ) digital-to-time converter (DTC) frequency-locked loop (FLL) jitter
الوصول للمادة أونلاين:	https://ieeexplore.ieee.org/document/11275669/
الوسوم:	إضافة وسم لا توجد وسوم, كن أول من يضع وسما على هذه التسجيلة!

A 8.9 to 10-GHz &#x2212;97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process

مواد مشابهة

A 8.9 to 10-GHz −97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process