Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation

A fractional-N frequency synthesizer with low total jitter [e.g., &#x003C;50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and inj...

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書誌詳細

主要な著者:	Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski
フォーマット:	Artigo
言語:	Inglês
出版事項:	IEEE 2024-01-01
シリーズ:	IEEE Open Journal of the Solid-State Circuits Society
主題:	All-digital phase-locked loop (ADPLL) delta–sigma modulator (DSM) digital-to-time converter (DTC) fractional-N integral nonlinearity (INL) millimeter-wave (mmWave)
オンライン･アクセス:	https://ieeexplore.ieee.org/document/10707313/
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